1. Field of the Invention
The present invention relates to semiconductor memory devices and more particularly to a circuit for applying a stress voltage to memory cells in the device during testing of the device.
The present invention claims priority from Korean Patent Application No. 10167/1995 which is incorporated herein by reference for all purposes.
2. Description of the Related Art
As semiconductor memory devices have become more and more highly integrated, the occurrence of manufacturing defects has increased. While it is difficult to salvage a chip when defects occur in peripheral circuits, it is possible to do so when defects occur within a memory cell array by replacing the defective memory cell with a redundant memory cell. Therefore, it is important to detect defective cells in the early testing stages. There has been a strong demand for such testing techniques. However, screening techniques for defective cells which have been developed can not detect all the defective cells. Generally, failures due to defects within a memory cell array are divided into a hard cell defect which can be detected in a sorting test, and a soft cell defect which is not detected in an early stage test and yet gradually degrades in the presence of electrical fields or temperatures which are within operating specifications of the device. Ideally, screening techniques should be able to detect both the hard and soft cell defects.
In a conventional technique, all arrays are selected simultaneously in a test mode and then a stress voltage which is as high as 1.4 to 2 times the normal memory operating voltage Vet is applied to the arrays. Thereafter, defective cells are detected by checking whether or not any cells prevent normal operation of the device. That is, in the case of random access memories and mask read only memories, the status of the cells is determined by checking whether or not they operate normally in a refresh operation or when operating with a low or a high Vcc. Typical types of cell failures included a gate oxide breakdown or a junction breakdown. However, an EPROM determines binary data according to the charge applied to a floating gate, by using the hot carrier or Fowler-Nordheim tunneling, when programming or erasing data. Because cell data is easily affected by the charge, even though the gate oxide or junction leakage is weak, a defective cell may fail more easily. That is, even weak charge leakage in a bake test, burn-in test or disturb test may change data. However, when testing by selecting all arrays simultaneously and applying the stress voltage thereto, if there are a plurality of soft cell defects and hard cell defects which may cause a stress voltage drop within the array, a substantial drop in the stress voltage is caused by a hard defect cell. The stress voltage is therefore not high enough to detect a soft cell defect. This makes it difficult to accurately screen soft cell defects. Therefore, if the soft cell defects do not fail in an early stage of the test but fail gradually through the electrical stress, bake, burn-in or reliability tests, yield is reduced. Further, in order to repair the soft cell defects, an additional screening step is required, resulting in increased testing time and deteriorating the efficiency of operation. In the case of EPROM and EEPROM, there is a greater possibility of generating soft cell defects and hard cell defects in a cycling test in which the memory device is repeatedly erased and programed.